Aldec launches HES-DVM Proto “Cloud Edition”
Henderson, NV, United States – June 2, 2021 – Aldec, Inc., a pioneer in mixed HDL simulation and hardware-assisted verification for FPGA and ASIC designs, has launched HES-DVM Proto Cloud Edition (CE). Available through Amazon Web Service (AWS), HES-DVM Proto CE can be used for FPGA-based prototyping of SoC / ASIC designs and focuses on automated design partitioning to dramatically reduce setup time when up to four FPGAs are required to accommodate a design.
HES-DVM Proto CE can be used with Aldec’s HES pre-silicon prototyping boards, third-party boards, or users of in-house developed platforms and costs only $ 2,359.50 per month, so it’s ideal for use on projects with short prototyping phases. Alternatively, for companies with multiple projects underway, HES-DVM Proto CE is a great way to assess HES-DVM before committing to investing in the traditional licensed version.
“We introduced HES-DVM’s automatic FPGA partitioning function in 2019”, recalls Zibi Zalewski, Managing Director of Aldec’s Hardware division, “And it proved to be an immediate success as it allows users to automate the configuration of multi-FPGA design prototypes, reducing errors and saving a lot of time.”
Zalewski goes on to say that current SoCs are designed to meet many ASIC-like requirements, such as power efficiency, clock distribution, gate, and hierarchical bus architecture to ensure the highest performance, avoid blockages and minimize power demand peaks.. He adds, “Meeting these many ASIC requirements requires an architecture and design hierarchy that rarely fits easily into an FPGA-based prototyping platform due to the way resources must be allocated and interconnections made. Changing the design hierarchy in favor of the prototyping step is to be avoided, so it is important to have a tool that will automatically create balanced partitions – by selecting and placing module instances in the design hierarchy. original. The tool should also provide a fine degree of controllability and advanced analysis for synchronizing critical paths or evaluating alternative FPGA partitioning schemes and their impact on interconnects.
Equally important, Zalewski explains, is the automatic management of I / O connections with LVDS-based serializers to resolve problems caused by a limited number of FPGA I / O.
“All of the above designer wishes are met by our HES-DVM, which is a well-established and reliable EDA tool. Now, HES-DVM Proto CE makes this extremely powerful capability available – affordably and in an easily scalable way through the “on-demand” cloud operating model – to engineers desperate to reduce their input of design prototypes. ASIC and SoC both. “
HES-DVM Proto CE comes as an out-of-the-box AWS AMI environment with DVM partitioning software and Aldec’s proven SyntHESer fast synthesis engine. Users only need to copy the RTL design source code and can begin partitioning immediately, avoiding typical computer or software maintenance issues. The highest level of security is provided by Amazon AWS and the strict AMI qualification process for AWS Marketplace.
HES-DVM Proto CE can be used for prototypes containing up to four Xilinx FPGAs – found on standard prototyping boards like Aldec HES, third party or even developed in-house FPGA boards that are custom designed for a given project and deliver features not available on commercial platforms. If a later revision of the project grows and requires more than four partitions, there is a transparent migration path to the on-premises (standard licensed) version of HES-DVM, which can support an unlimited number of FPGAs.
Zalewski concludes: “HES-DVM Proto CE is aimed at medium-sized projects with budgets to match. In essence, we’ve made a very affordable version of an extremely powerful and fast EDA tool available to users who may not need to partition the design all year round.
HES-DVM Proto CE is now available for purchase.
Aldec launches HES-DVM Proto Cloud Edition (CE). Available through Amazon Web Service (AWS), the cloud-based tool can be used for FPGA-based prototyping of SoC / ASIC designs and focuses on automated design partitioning to dramatically reduce setup time.
About HES ™ prototyping
Aldec offers a portfolio of HES ™ prototyping boards based on the largest Xilinx FPGAs from the Virtex UltraScale +, UltraScale and Virtex-7 families. The cards are designed for easy expansion using the BPX backplane and standardized FMC and BPX daughter card connectors.
About HES-DVM-CE ™
HES-DVM Proto CE is the Cloud edition of the HES-DVM software product used for design compilation and partitioning into multi-FPGA prototyping platforms. It is available on the Amazon AWS Marketplace as an Amazon Machine Image (AMI) based on the Amazon Linux image as a base with Aldec HES-DVM software preinstalled. The HES-DVM Proto CE combines electronics design automation software for design partitioning and scalability of the Amazon Elastic Compute Cloud (Amazon EC2) compute platform.
Aldec Inc., headquartered in Henderson, Nevada, is a leader in the electronics design verification industry and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military / Aerospace solutions. www.aldec.com